embedded world North America 2026: four stops and a housing warning

embedded world North America runs September 22–24, 2026 at the Anaheim Convention Center. I will be there. It is a two-hour drive up the 5 from San Diego, which makes it the one major embedded show I can attend without an airport, and after last year — 3,800 attendees across 266 exhibitors, up 15% on the first edition — it has earned the day.

Before anything technical, a warning that costs people real money every year.

Book your hotel from the show’s own link, not from a phone call

Don’t fall victim to housing scams. Book your housing from our direct link on this website! — embedded world North America

The organisers put that notice on their own front page, and they put it there because the scam is routine. It is called room block poaching. Once the exhibitor and attendee lists start moving around, you get unsolicited calls and emails from an outfit calling itself the “official housing bureau” for the show. They are convincing. They know the dates, they know the venue, sometimes they know which booth you have. They offer a rate slightly under the block, they want a card number on the call, and then one of three things happens: the reservation does not exist, it exists at a hotel nowhere near the convention centre, or it gets cancelled a week out and your deposit is non-refundable.

The defence is simple and absolute: never give card details to anyone who contacted you first. Book here, which is the link on the show’s own site:

• Official housing: mmxreservations.com — embedded world NA 2026 block
• Registration: prereg.net/2026/ewna

If someone rings you claiming to be the housing bureau, hang up and go to the link above. The real bureau does not need to cold-call you, and no legitimate housing partner will pressure you to decide on the phone.

The show, in numbers

There is also a hackathon and robotics lab running alongside. The $55 expo pass is the best value on the list if you only want to put your hands on silicon and talk to field application engineers, which is most of what I go for.

Four stops on my list

STMicroelectronics — booth 5700

ST is showing the STM32N6, and it is the part I most want to see running rather than read about. On paper it is a departure from everything else wearing an STM32 badge: an 800 MHz Cortex-M55, ST’s own Neural-ART accelerator clocked at 1 GHz with close to 300 configurable multiply-accumulate units, 600 GOPS peak, and 4.2 MB of on-chip RAM. There is an image signal processor good for a five-megapixel sensor at 30 fps, an H.264 encoder, and 2D and 2.5D graphics accelerators alongside.

Two things about that specification matter more than the headline number.

First, 4.2 MB of internal RAM is the real news, not 600 GOPS. If a quantised model and its working buffers fit on-chip, you delete external SDRAM from the bill of materials and you delete a fast parallel memory bus from the board. I lay out multi-layer boards in Altium and KiCad, and I can tell you that removing a DDR interface removes a whole category of layout risk, EMC surprises and signal integrity work. That is worth more to a small production run than any GOPS figure.

Second, 600 GOPS is a peak, not a promise. ST quotes roughly 3 TOPS/W, which is genuinely good for a microcontroller, but the accelerator feeds through two 64-bit AXI buses and that bandwidth is shared. My question at the booth is not how fast the NPU goes. It is what happens to a hard real-time control loop on the M55 while the NPU is saturating those buses. I have spent most of thirty years writing interrupt-driven bare-metal firmware where timing is the requirement, and “the inference finished in 12 ms on average” is not an answer when a motor commutation deadline is 50 microseconds. If you are considering this part for anything that both looks at a camera and controls a mechanism, ask about worst-case interrupt latency under NPU load, and ask to see it measured.

The demos ST is bringing are sensible rather than flashy: an STM32N6 Discovery Kit running as a security camera, streaming video over Ethernet and pushing a JPEG notification when it detects a person, plus the X-NUCLEO-IKS5A1 doing voice activity detection and head-motion recognition from IMU data. The person-detection-to-notification path is the one I would watch end to end, because that is the shape of most real edge AI jobs: not continuous inference, but a cheap always-on trigger that wakes an expensive pipeline.

ST is also publishing a code for $40 off a pass — STMICR26118 — on their event page.

Nordic Semiconductor

Nordic has had a busy year, and most of it landed at the Nuremberg show back in March rather than being new for Anaheim. That is fine: it means the silicon is real and the kits exist, which is a better state to evaluate a part in than a launch slide.

The flagship is the nRF54LM20B — 2 MB of non-volatile memory, 512 KB RAM, up to 66 GPIO, high-speed USB, and an integrated Axon NPU that Nordic claims runs inference up to 15× faster than doing the same work on the Cortex-M33. It took Embedded Computing Design’s Best in Show at embedded world, and the development kit is now shipping.

But the part I find more interesting is at the other end. The nRF54LS05A and nRF54LS05B fill in the bottom of the nRF54L series: same 128 MHz Cortex-M33, same fourth-generation Bluetooth LE radio, 0.5 MB of NVM, and 64 KB or 96 KB of RAM respectively. They are for sensors, beacons and remotes — the unglamorous high-volume end.

What makes that worth attention is not the specification, it is the pin-to-pin compatibility across the series. I have been on the wrong side of this more than once: you pick a part, lay out the board, write the firmware, and then the feature list grows and you are out of RAM, or procurement finds the part on 40-week lead time. If your escape route is a pin-compatible sibling with four times the memory, that is a firmware rebuild. If it is not, that is a board respin, new fabrication, new bring-up, and a schedule you have already promised. Designing a board so it can accept three parts from the same series is one of the cheapest insurance policies in embedded work, and Nordic is one of the few vendors that makes it explicit across a whole range.

The other Nordic announcement I would actually use is Fuel Gauge v2.0 for the nPM1300 and nPM1304 power management ICs. It adds state-of-health estimation alongside state-of-charge, with fleet-level battery analytics surfaced through nRF Cloud using Memfault. State-of-charge is the easy problem and everybody ships it. State-of-health is the one that tells you a deployed fleet is quietly aging toward a warranty event. On a generator control system I built, the thing the customer needed was never the instantaneous number, it was the trend.

One caveat worth raising at the booth: the fleet analytics run through Nordic’s cloud and Memfault. That is an architecture decision and, for a lot of my clients, a contractual one. If your device ships into somewhere that will not tolerate a third-party cloud dependency, find out early what the on-device API gives you without it.

u-blox

u-blox brought the first products on its F11 platform to market at the start of July, and the number that matters is 7 mW.

That is the figure in LEAP mode — Low Energy Accurate Positioning — with three constellations running, and it is down from 12 mW on the MAX-M10N it succeeds. The launch covers the dual-band UBX-F11270-KB and UBX-F11170-CC chips on L1 and L5 across GPS, Galileo, BeiDou, QZSS and NavIC, a single-band M11 sub-family including the UBX-M11070-KB and the MAX-M11N module, and the EVK-F112 evaluation kit. A dual-band MAX-F11N module is slated for Q4 2026. Accuracy is quoted at 1.0 m CEP with SBAS, 1.5 m without, and the WL-CSP package is 2.39 × 2.39 mm.

The cleverest feature is Selective L5, which switches between L1-only and dual-band depending on what the signal environment looks like. L5 buys you real multipath resilience in a city, and it costs power you do not want to spend in open sky. Making that automatic is the right call.

Now the part that a datasheet will not tell you, and the reason I will be at this booth rather than just reading the brief. Cutting run current from 12 mW to 7 mW does not cut your energy budget by 42%. Cold-start time to first fix is still 28 seconds; hot start is 2 seconds. On a duty-cycled asset tracker, the energy per fix is dominated by how long the receiver is awake trying to get that fix, not by how many milliwatts it draws while awake. A tracker that wakes cold four times a day and takes 28 seconds each time is in an entirely different place from one that keeps enough ephemeris to hot-start in two. So the questions I want answered are about the aiding strategy: how much state can you retain across sleep, what does retaining it cost, and what is the realistic distribution of TTFF in a device that spends its life in a shipping container.

Two honest reservations. LEAP is proprietary rather than an open standard, which is a lock-in consideration for a product you expect to build for a decade. And production is Q4 2026, with engineering samples now — so this is a design-in conversation for next year’s hardware, not a part you drop into a board going to fabrication this month. Worth knowing before you build a schedule around it.

u-blox has also been testing the ZED-R20P module with its NavPRISM technology for interference detection and mitigation, which given how much cheap GPS jamming is now in the wild is a subject I would like to hear them talk about candidly.

Performance Software — booth 6117

The one stop on my list that sells no silicon, and possibly the most useful.

Performance Software does DO-178C avionics software certification out of Phoenix — close to thirty years, more than 500 programs, design assurance levels A through E, working in C, C++, Ada and autocode generated from MATLAB/Simulink and SCADE.

I want to talk to them for two reasons. The first is that I have watched the gap between “it works on the bench” and “it is certifiable” swallow schedules whole, and it is nearly always discovered late. Requirements traceability, structural coverage analysis and tool qualification are not things you retrofit onto a finished codebase; they are things the codebase has to be built to accommodate from the first commit. A team that has run 500 programmes has seen every way that goes wrong, and an hour of that at a trade show is cheap.

The second reason is autocode. A great deal of control work starts life in Simulink, because that is where the control engineers are, and generated code is exactly where certification arguments get expensive and contentious. If any part of your product might eventually move toward a regulated market — avionics, medical, functional safety — the cost of asking these questions now against discovering the answers during an audit is not close.

It also overlaps my own expert witness work. When a system fails and ends up in front of a court, what gets examined is the evidence trail: what the requirements said, what was verified, and what was signed off. The disciplines that make software certifiable are the same disciplines that make it defensible.

What I am actually shopping for

Three things, in order.

Deterministic behaviour under AI load. Every vendor on the floor will have an NPU story. Very few will have measured worst-case interrupt latency while that NPU is running. The ones that have are the ones I will specify.

Second sources and pin compatibility. After the last several years, I design boards on the assumption that at least one part on them will become hard to buy. I want to know a vendor’s migration path before I want to know its benchmark.

Honest power numbers. Not the sleep current on the front page of the datasheet. Energy per useful operation, measured on real duty cycles, with the radio and the fix time included.

If you are going to be in Anaheim and any of that is your problem too, I am happy to meet at the show. Drop me a note and we will find a time. And book your room from the official link.